1. Field of the Invention
The present invention relates to materials, apparatus and processes used in the manufacture of printed circuit boards. The invention particularly relates to the improvement in registration between layers within multi-layer printed circuit boards (PCB's) by novel methods and apparatus. In greater particularity, the present invention relates to improved methods and apparatus for the correction of conductor feature placement error in the fabrication of PCB inner layers. In particular, the invention relates to processes and apparatus which improves inter-layer registration and thereby also improves manufacturing yields.
2. Background of the Art
Multi-layer printed circuit boards (multi-layer PCB's) are one of the most common forms of electronic interconnection means. Multi-layer PCB's may be manufactured by stacking up to twenty (20) or thirty (30) layers (each layer is referred to as an inner layer). Each of the inner layers has its own, previously generated conductor or electronics pattern. The electronics pattern in each of the layers may eventually be electrically connected to the electronics pattern in another layer (not necessarily an adjacent layer) by an interlayer connection, such as a pin, post or, by way of a hole (e.g., a conductive metal plated hole used to interconnect given pads between two or more layers), or any other conductive element that passes from an inner layer to another inner layer, from one conductor site to another conductor site. One of the major difficulties in the manufacture of multi-layer PCB's is the need to match or register the conductor traces or the conductor sites of inner layers which are to be electrically connected. The general field of this problem is referred to as inner-layer registration.
The registration problem may involve general misalignment of the entire conductor pattern, lack of registration of individual elements in the conductor pattern, misregistration of conductive pads, and insufficient registration of conductive sites (e.g., often referred to as pads) within the pattern. In actuality, although is not believed to have been specifically identified before the present invention, the lack of registration of conductor sites (the actual points within the conductor pattern which are to be connected to other conductor sites in other inner layers) is the primary problem in inner-layer registration. If the entire conductor pattern of two inner layers to be connected were out of alignment, except for the conductor sites, no correction would be necessary. If only the conductor sites within a pattern were out of alignment, but all other elements were in perfect register, the lack of registration would not be tolerable, and the interlayer connection of the conductor patterns would be likely to fail.
Registration between layers in a multi-layer PCB has been approached in many ways. A good summary of the error sources and their effects associated with multi-layer registration is given in the article Inner-layer registration error--causes, effect & cure by Tom Paur of American Testing Corporation.
This article discusses, among other issues, contributors, which affect the process control for the PCB fabricator. According to this article, there are five process variables that contribute more than 90% of all registration problems:
1. Growth/shrinkage of core material during fabrication. PA1 2. Artwork--plotter out of size or square and film instability. PA1 3. Image transfer--punching error or side-to-side alignment error. PA1 4. Skew during lamination--"squish." PA1 5. Drilling error. PA1 Type of material construction (thickness of material and copper, composition of material, weave, amount of resin, direction of weave, etc.). PA1 Processing temperatures and pressures. PA1 Mechanically induced stresses from shearing, scrubbing, punching that may be relieved during subsequent processes. PA1 Amount of copper removed during etch. PA1 The dominant x-y orientation of the remaining copper. PA1 Construction layout of panel, i.e., power/ground on one side of the core, signal on the other side, or signal both sides, or where in the stack a core is located (3-4 versus 5-6, etc.). PA1 The tooling pattern is punched in the inner layer after etching. All material movement resulting from artwork instability, etching, black oxidizing, etc. is compensated for by offset and global scale. PA1 Tooling holes and/or slots that are punched before etching are subject to movement during the etching process. This results in buckling or stretching of the inner layers when pinning on the lamination plates which can cause misregistration. Post-etch punching eliminates this problem, insuring an accurate match between the inner-layer tooling holes and the lamination plates. PA1 Slots and/or holes punched in the laminate prior to etching are subject to copper loss around the tooling. Post-etch punching allows copper to remain around the tooling holes for additional strength during lamination. PA1 Some post-etch machines have the added advantage of providing statistical process control data (SPC). The SPC data shows the difference in mils between the inner-layer targets and the machine-reference targets. This information can be collected and used to evaluate prior processes as well as reaction of different materials. A tolerance window can also be set, specifying a maximum allowable material shift. Inner layers outside this range would either be automatically rejected or could be grouped with layers of similar movements. PA1 a) comparing the scanned map to the initial map for that layer and creating an error or deviation vector map from a comparison between the initial map and the scanned map, and then correcting the initial map to an adjusted map, the adjusted map being altered to correct the deviations identified in the comparison between the initial map and the scanned map, so that a next first inner layer made by the defined process on the defined apparatus will produce a conductor pattern having less deviation of location of conductor sites thereon; PA1 b) producing an initial set of at least two layers to be formed into a multilayer PCB, comprising a first and second layer made by a defined process on a defined apparatus (artificially termed "a first inner layer" and "a second inner layer," even though each layer does not have to be the first or second layer in any particular direction within the PCB); comparing the initial maps of only one of the first and second layers with only one of the scanned map of the first and second layers respectively, and then correcting the initial maps of only one of the first and second layers to form an adjusted map of only one of the first and second layers, the adjusted map being altered to correct deviations identified in the comparison between the initial map of only one of the first and second layer and the scanned map of only one of the first and second layer, so that a next first inner layer and a next second inner layer made by the defined process on the defined apparatus will produce a conductor pattern having less deviation of location of conductor sites as between the next first and second layers; PA1 c) producing an initial set of at least two layers to be formed into a multilayer PCB, comprising a first and second layer made by a defined process on a defined apparatus (artificially termed "a first inner layer" and "a second inner layer," even though each layer does not have to be the first or second layer in any particular direction within the PCB); comparing the initial maps of each of the first and second layers with the scanned map of the first and second layers respectively, and then correcting the initial maps of the first and second layers to adjusted maps of the first and second layers, the adjusted maps being altered to correct deviations identified in the comparison between the initial maps and the scanned maps, so that a next first inner layer and a next second inner layer made by the defined process on the defined apparatus will produce a conductor pattern having less deviation of location of conductor sites thereon. The ability to maintain the sites in register with each other with regard to through holes, posts, and other linear or vertical features is extremely important in the manufacture of these circuits; PA1 d) producing an initial set of an entire number of inner layers to be formed into a multilayer PCB, comprising an entire number of layers made by a defined process on a defined apparatus; comparing the initial maps of each of the entire number of inner layers with the scanned maps of the entire number of inner layers, respectively, and then correcting the initial maps of the entire number of inner layers, the adjusted maps being altered to correct deviations identified in the comparison between the initial maps and the scanned maps, so that each of the next entire number of inner layers made by the defined process on the defined apparatus will produce a conductor pattern having less deviation of location of conductor sites between adjacent layers; PA1 e) scanning a laminated multilayer printed circuit board to develop an image of the arrangement of at least two inner layers within the PCB. Using the x-ray image (which may be digitized for compatibility with a digital imaging system) to provide an image (data set of an image) of the inner layer features (e.g., the nubs, electrical or electronic features or electrical contact points) after the at least two inner layers have been laminated, enabling compensation for the next layer(s) or for re-registration of the next set(s) of the inner layers in the imaged laminate; this will allow for compensation in the next set(s) for deformation caused by the lamination process as well. Again, the prior art for this type of x-ray imaging is the reading of only four fiducials (at fixed points within the laminate) and then compensating by a linear scale modification in the outer layer imaging; the present system and process allows for correction of subsequent inner layer imaging to offset any and all errors, including lamination error; and PA1 f) repeatedly producing an initial set of an entire number of inner layers to be formed into a multilayer PCB, comprising an entire number of layers made by a defined process on a defined apparatus; comparing the initial maps of each of the entire number of inner layers with the scanned maps of the entire number of inner layers, respectively, on an area-by-area basis (including the actual possibility of a pixel-by-pixel basis); determining the amount and direction of deviations in each area (e.g., even a pixel); comparing the amount and direction and deviation in each area (e.g., pixel) with parameters in the original map at least including: PA1 1) size of features in the initial image (size including length, width and depth), and PA1 2) location of the element on the layer,
The two largest factors from this group are material growth/shrinkage, which typically contributes more than half of the total error, and artwork error. The rest of the error is distributed between the remaining factors. These factors will vary somewhat from shop to shop depending on the type of equipment, processes and process control, but they are reasonably consistent across the industry.
Further the said article discusses ways of dealing with material growth/shrinkage. Material growth/shrinkage is the most significant factor in registration control. It is also the easiest to identify, measure and control. The process variables that affect material growth/shrinkage include:
______________________________________ Total Registration Error From All Causes 60% 15% 25% ______________________________________ Incorrect compensation All other causes Artwork error caused by (scaling) of artwork for plotter, punching and growth/shrinkage of core environmental effects material during fabrication ______________________________________
According to the article, each of these factors will have a very predictable effect on growth/shrinkage when applied in a given combination, making material movement one of the most manageable of the variables. Being able to identify and manage the specific contribution of each factor to the total error allows the fabricator to dramatically reduce the total registration error.
As can be seen from the cited article and from the following description of inner-layer registration methods, the standard registration error is well understood and dealt with.
Most common inner-layer registration systems can be divided into two major methods: Pre-exposure registration method and post-etch punching registration method. The "pre-exposure" system has been the accepted method for multi-layer registration since the inception of multi-layers.
In a typical "pre-exposure" registration system, layer-to-layer registration is achieved by aligning inner-layer artwork to a drilled master panel (first article) and punching the artwork with the tooling slots or holes. The tooling punched in the artwork matches the tooling that is punched in the inner-layer laminate. The artwork and laminate are pinned together and exposed.
The demand for tighter circuitry on thinner and larger panels brought about the post-etch punch systems to the industry.
The post-etch punching method is described in U.S. Pat. No. 4,829,375 by Alzmann et al. The method includes locating a target on a printed circuit board laminate having a circuit pattern etched thereon and utilizing the target to locate the laminate in a punching device. Two such targets are employed and the laminate is adjusted in the X and Y directions as well as rotationally to bring the target into prescribed relationship with reference markings whereby to locate the holes precisely in the laminate whereby to facilitate stacking of the same. In related apparatus, two television cameras are employed to operate with two targets to feed data into a microprocessor, which generates signals to cause an alignment of the laminate to be punched. With respect to punching mechanisms, special techniques are employed to locate the centers of the targets to that these centers can be aligned with cross hairs to take into account the deviations possible in the configurations of the targets.
Post-etch punching of inner layers offered the following advantages as compared to pre-exposure methods:
Other related prior art are U.S. Pat. Nos. 5,548,372 and 5,403,684 by Schroeder et al. These inventions describe a tooling apparatus designed to provide accurately aligned printed circuits on both major sides of a printed circuit board layer. Another apparatus includes patterns formed on glass masks attached to frames incorporating alignment pins and slots. The patterns include registration marks for alignment during manufacture of the apparatus. During use, the apparatus allows accurate alignment of patterns on both sides of a PCB layer.
Regardless of the method utilized for inner-layer registration, the task of inter-registering the inner layers became increasingly difficult as the average number of layers increased and the conductor feature density became larger.
Looking at the registration task analytically, it can be divided into two categories. The first can be called offset and rotation stack-up errors. Registration error coming from misplacement or misorientation of an inner layer relative to the reference stack-up location. The second category is linear and non-linear scaling errors resulting from the dimensional changes, which the inner-layer panels undergo through the various fabrication processes from imaging through etching and lamination. Both the inherent variations within chemical processing and variations in the imaging process (particularly from edge phenomena or light scattering) can contribute to these errors. While linear scaling error may be characterized by a single correction factor per axis for a given type of layer, non-linear scaling errors require a more complex correction scheme. Starting from second order non-linearity which requires two correction factors through higher degrees of non-linearity, which require a number of correction factors equal to the degree of non-linearity to the most complex case where the required correction factor is as complex as the image file itself.
The widely applied linear scaling error correction, as previously described in the prior art, is generally practiced using experience-based prediction. The shop collects scaling error information for each type of material construction (thickness of material and copper, composition of material, weave, amount of resin, direction of weave, etc.) to build a statistical error database. The measurement of the errors is done on four specifically made tooling targets on each side of the inner-layer panel. Based on this information, a single linear scale correction factor for each of the layer types is determined. This scale factor is then applied to the artwork plotting according to the type of layer, which will be used for the job. The prediction does not always provide adequate correction for complex or sophisticated panels, whereupon a second artwork would have to be prepared after running the first article. This is since the linearity of the dimensional change of the layer depends on the post-etch copper distribution on the layer. The PCB design engineering is therefore required to design the layout of the panel such that it is symmetrical with balanced copper spread to ensure maximum uniform dimensional change so that linear distortion correction only would be sufficient. But some complex designs have too many constraints to conform to this linear scaling rule.
With the conductor features getting finer, and the average number of layers getting higher, the criticality of the correction of non-linear scaling becomes more significant. It is estimated that for feature of 3-mil line/space and smaller, better registration accuracy would be required so the local non-linear distortion would become significant in the registration error budget. Moreover, complex PCB designs do not allow for even distribution of post-etch copper, resulting in non-linear dimensional change. It is estimated that correction of the non-linear error would be mandatory for acceptable yields for such multi-layer board production technologies.
The non-linear scaling error correction presents a tough challenge, since the correction required is location dependent. The more precise the correction needs to be, the more data on the etched layer conductor features would have to be collected. The extreme case would be where the non-linearity is of very high degree, necessitating the geometry of the whole layer to be scanned in. A precise scanning means is not very common in this industry, hence its addition would have cost impact. No wonder why such correction algorithm has never been applied so far. Its application was too complex and expensive, while the errors were not critical for the work that has been done so far.
The tools commonly used today in PCB shops to determine the linear scale errors are the four CCD cameras in the post-etch punch system for separate layers, and the X-ray system for boards after lamination. All those tools are aimed to check for linear scale errors only, since they can only measure a limited number of points on the layer being measured. Few papers published by large PCB manufacturers refer to linear error correction. The reports from these companies also mention the etch and lamination errors as the most significant error of all the process stages.